N bit Concurrent SEU recognition and rectification for Hybrid NVSRAM Cell

The main project confronted through Hybrid NVSRAM cell with soft error tolerance. The proposed NVSRAM cell comprises of a 6T SRAM core and a Resistive RAM (RRAM), made of a 1T and a Programmable Metallization Cell (PMC). The proposed cell has simultaneous mistake recognition called as concurrent error detection (CED) what's more, rectification (error correction) capacities. CED is proficient utilizing a dualrail checker, while it is refined (corrected) by using the restore operation; information from the non-volatile memory component is replicated back to the SRAM core. The dual rail checker uses two XOR doors each made of 2 inverters and 2 ambipolar transistors, henceforth, it has a hybrid nature. The reproduction results demonstrate that the proposed plan is exceptionally proficient as far as various figures of merits.