VLSI implementation of systolic array for discrete waveelet transform

This paper presents a VLSI implementation of Systolic architecture for discrete wavelet transform (DWT). This architecture consist of Input delay unit, filter, register bank and control unit. This performs the calculation of high pass and low pass coefficients by using only one multiplier. This architecture have been simulated and implemented in VLSI. The hardware utilization efficiency has been more than 85%. The systolic nature of this architecture corresponding to a clock speed of N MHz. Optimized area, time and power obtained from this architecture for various devices.