Design, charaterization, comparison of ultra low power high speed CMOS inverter at 90nm/65nm/45nm/32nm/22nm/16nm

Numerous efforts have been made to minimize power dissipation and to balance the tradeoff between power, area, and delay at 90nm/65nm. Paper presents a bit forward in this direction and tries to concentrate on power as well as on performance. In the present work simulation of CMOS inverters below threshold at 16nm/22nm/32nm/45nm/65nm/90nm using TANNER tool is done and tries to optimize delay and noise along with power. Also the device size calculated in each case and for achieving ultra Low power, voltage scaling and operation in threshold are utilized. STACK is also reviewed and can be used where delay and area not matters. Further optimization of the results is done by employing DTMOS. This work tries to maintain delay in limits with continuous scaling down the technology files and the supply voltage.