Systematic Design of High-Speed and Low-Power Digit-Serial Multipliers VLSI Based

Terms of both latency and power Digit-serial implementation styles are best suited for implementation of digital signal processing systems which require moderate sampling rates. Digit-serial architectures obtain using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, an alternative approach for the design of digit-serial architectures is presented based on a novel design methodology. This methodology permits bit-level pipelining of the digit-serial architectures by moving all feedback loops to the last stage of the design. This enables bit-level pipelining of digit-serial architectures, thereby achieving sample speeds close to corresponding bit-parallel multipliers with lower area. This increased sample speed can be traded with reduction in power supply voltage resulting in significant reduction in power consumption. The proposed approach is applied to the design of various multipliers which form the backbone of digital signal processing computations. The results show that for transformed multipliers with smaller digit sizes (_4), the singly-redundant multiplier consumes the least power, and for larger digit sizes, the type-I multiplier consumes the least power. It is also found that the optimum digit size for least power consumption in type-I and type-III multipliers is _p2W, where W represents the word length. Among the bit-level pipelined digit-serial multipliers, it is found that the redundant multiplier offers the best choice in consumption The proposed digit-serial multipliers consume on average 20% lower power than the traditional digit-serial architectures for the non pipelined case and about 5–15 times lower power for the bit-level pipelined case.