Design and development of AXI based multi channel interrupt controller2

Processors and peripherals usually communicate with each other with the use of interrupt. Number of peripherals and processors are increasing and the processors have limited interrupt ports which is far less than the total interrupt signals of peripherals and other co-processors in a System-on-Chip (SoC). Flexibility of interrupt controller is more and more concerned with the development of multi-million gate SoC. A configurable multichannel interrupt controller is proposed to solve this problem. Interrupt priority is configurable for processor by accessing registers through AXI (Advance extensible Interface) interface. The AMBA3 AXI is chosen protocol defines a unidirectional channel architecture, which enables the efficient use of register slices to pipeline the connection for higher speeds, or to enable the use of multiple clock domains for low power Combination interrupt is also realized for one Interrupt Service Routing (ISR) to service multiple interrupts at a time. Up to 60 interrupt inputs and 12 interrupt channels are supported in This design and by using this design in many Embedded system design applications and by this in one soc we connected number of peripherals device in one system on chip to increases the performance of the system. Verilog is a hardware description language (HDL) used for simulation of proposed algorithm.