Low power cellular automata based triple byte error correcting code

A cellular automaton (CA) has already established its novelty for bits and bytes error correcting codes (ECC). The current work identifies weakness and limitation of existing CA-based byte ECC and proposes an improved CA-based triple byte ECC which overcomes the identified weakness. The code is very much suited from VLSI design viewpoint and requires significantly less hardware and power for decoding compared to the existing techniques employed for Reed–Solomon (RS) Codes. Also it has been shown that the CA-based scheme can easily be extended for correcting more than three byte errors.