Broad band receiver design on FPGA

In this paper, we present a new receiver architecture, which is motivated by optimum detection of Amplitude Shift Keying (ASK) signals in the presence of Tikhonov-distributed residual phase error due to the phase-locked loop (PLL)-aided phase tracking scheme. And a computationally-efficient(C-E) receiver architecture is proposed to reduce the receiver architecture. Performances on AWGN and fading channels are evaluated by bit error rate (BER). The simulations show that BER performances follow those of the optimum receiver over a wide range of signal-to-noise ratio (SNR), while outperforming a standard coherent receiver operating in the presence of residual phase error by more than 2 dB. And by using System Generator, the C-E receiver architecture is implemented on Field-Programmable Gate Array (FPGA) under AWGN channel, which follows the simulation results.