*Associate Professor, Department of ECE, PSNA college of Engineering and Technology, Dindigul, Tamil Nadu, India
**Professor, Department of CSE, PSNA college of Engineering and Technology, Dindigul, Tamil Nadu, India
Online published on 11 November, 2013.
Filtering is one of the main operations in signal processing. The efficiency of the filter mainly depends on multiplier and adder. The modulo 2n+ 1 multiplier and adder are used to design modulo 2n + 1 FIR filter architecture which is useful in applications like Residue Number System, Digital Signal Processing applications and cryptographic algorithms. In this multiplier [1], one operand uses weighted representation and another operand use diminished-1 representation. The new multiplier reduces the number of partial products which in turn reduces the operational time and power. Modulo 2n + 1 adder [2] can produce modulo sums within the range {0, 2n}, which is more than the range {0, 2n − 1} produced by existing diminished-1 modulo 2n + 1 adders. Since both units are designed effectively, the proposed FIR filter will be efficient.
FIR filter, dimnished-1 representation, residue number system, modular arithmetic, modular multiplier
