Fault detection in memory application using Majority Logic Decoder/Detector

In recent years, memory cells have become more liable to soft errors. This must be protected with effective error correction codes. Majority logic decodable codes are suitable for memory applications because of their capability to correct large number of errors. Conversely, they increase the average latency of the decoding process because it depends upon the code size that impacts memory performance. Another method of decodable logic is Majority Logic Decoder/Detector which reduces the decoding time, memory access time and area utilization. The drawback of this method is that it does not detects the silent data error and it consumes the major area of the majority gate. Low-Density Parity-Check (LDPC) codes are used for error correction, because of their fault-secure detector capability. In this paper, an enhanced majority logic decoder/detector (MLDD) is proposed to detect silent data error (SDE) using additional logic and in order to reduce the area of the majority gate, by using sorting network. Thus, the proposed Method reduces the decoding time, area and also power consumption. Index terms - Error correction codes, Soft errors, Memory, Majority logic decoder/detector, Low-density parity check (LDPC) codes, Silent Data Error (SDE), Sorting network.