Design and implementation of systolic architecture for adaptive FIR filter

In most of the real time digital signal processing applications like FFT, digital filters etc, multiplication is one of the important operation, which decides the speed of the algorithm. In order to perform matrix multiplication at a greater speed, conventional multipliers are not suitable to achieve the required task. In order to address the above problem and in order to boost up the speed of matrix multiplication, systolic architecture is proposed. The DLMS adaptive algorithm minimizes approximately the mean square error by recursively altering the weight vector at each sampling instance. Here systolic architecture is used to obtain minimum mean square error and updated value of weight vector. Systolic architecture is an arrangement of processor where data flows synchronously across array element.

This project demonstrates an effective design for adaptive FIR filter driven by DLMS algorithm using Systolic architecture, synthesized and simulated on Quartus-II tool in very high speed integrated circuit hardware description language (VHDL) and Field Programmable Gate Arrays (FPGAs). Here, by combining the concept of parallel processing and pipelining into systolic architecture, increases the speed of computation.