Control Flow Exploration and Optimization of Superscalar Processor

— Design of a microprocessor involves consideration of an optimal microarchitecture for a given objective function and a given set of constraints. Superscalar processing is the latest in along series of innovations aimed at producing ever-faster microprocessors. By exploiting instruction-level parallelism, superscalar processors [1] are capable of executing more than one instruction in a clock cycle. The architectural design of super scalar processor involves a lot of trade off issues when selecting parameter values for instruction level parallelism. The use of critical quantitative analysis based upon the Simple Scalar simulations is done to select optimal parameter values for the processor aimed at performance improvement. This paper aims at finding optimal values for the branch prediction for super scalar processor and determines which processor parameters have the greatest impact on the performance of the system.