International Journal of Management, IT and Engineering
  • Year: 2018
  • Volume: 8
  • Issue: 10

New High Performance Low Power Carry look Ahead Adder based on Fin FET Using MTCMOS Technique

  • Author:
  • Anand Kumar Gupta, Raghvendra Singh
  • Total Page Count: 18
  • Page Number: 25 to 42

*Research Scholer, Microelectronics & VLSI Design, Rama University, Uttar Pradesh, Kanpur, India

**Assistant Professor, Microelectronics & VLSI Design, Rama University, Uttar Pradesh, Kanpur, India

Online published on 18 October, 2019.

Abstract

In this paper we have designed a carry look adder circuit using CMOS technique, the low power and reduce Ground Bounce noise Carry look Ahead Adder based on FinFET has been proposed. A carry look ahead adder improves the speed by reducing the time required to solve carry bits. Carry-look ahead adder is a major functional block in arithmetic logic unit due to its high speed operation. The arithmetic logic unit has been widely used in microprocessor systems and mostly in processing modules of embedded systems. As the speed of the circuit increases the most important unwanted parameter exhibited by the circuits is ground bounce noise. In this chapter, we have proposed a modified Carry look Ahead Adder based on based on FinFET using multi-threshold CMOS technique. Here we use MTCMOS technique to evaluate standby leakage current, power and ground bounce noise. All the simulation in this paper has been carried out using Empyrean Aether” tool at 22nm technology at various voltage and temperatures.

Keywords

FINFET technology, Leakage current, Leakage power, Full adder