Design simulation of latch type voltage sense amplifier in low power and high speed operation for SRAM application

For an accurate sense operation, all nodes in the sense amplifier must be driven or equilibrated, earlier to clocking, to known voltage. For lowest power, it is needed that there are no DC paths from VDD to ground except during switching times. Also for a good comparison, the sense amplifier shouldn't have a memory of previous sensing operations. So we design sense amplifier with Removing Sense Amplifier Memory. In this paper we have propose and simulate low Power and great performance voltage latch Sense Amplifier for CMOSSRAM using VLSI design Technology i.e. primarily the plan of sense amplifier is designed & simulated using DSCH3. Sense Amplifier analyzed using MICROWIND3 in 65nm technology. Our effort is to diminish power consumption and expand the performance of sense amplifier. The results of simulation display that the proposed voltage latch sense amplifier design has benefit as compare to the conventional & improved conventional latch-type sense amplifier, based on 1.0V/65 nm CMOS technology. Proposed scheme improves sensing delay and also reduces power consumption.