Power Gating technique for leakage Power Reduction in Sequential Circuit

Portable and hand-held devices are significant now a days. So, leakage power reduction has emerged as the primary concern of today's VLSI designers. This leads to the concept of power gating methods to reduce the leakage power. Subclock (SCPG) and Stacking methods of power gating techniques are employed to reduce leakage power in the literature. To attain a better leakage power and improved peak power values, here a modified Subclock (MSCPG) method of power gating is proposed. The proposed method has 1bit Comparator for combinational circuit and D flip-flop for sequential circuit. The performance of the MSCPG method is analyzed in a sequential 4 bit SISO (Serial in Serial out circuit) using Cadence 180nm technology tool. The MSCPG method shows an improved performance than the other power gating methods.