1Student, ECE Department, Saveetha School of Engineering
2Associate Professor, ECE Department, Saveetha School of Engineering
Online published on 16 January, 2018.
A modified positive feedback adiabatic logic (MPFAL) for ultra-low power adder architectures are proposed in this paper. They are implemented in CMOS 90nm Generic Process Design Kit (GPDK) technology library. The main objective of the proposed technique is to minimize the Power consumption of a full adder using Modified Positive Feedback Adiabatic Logic. The proposed adders can be used in ultra-low power digital circuits operated at higher frequencies. These adders were simulated using Cadence Virtuoso Analog Design Environment (ADE) Electronic Design Automation Tool (EDA). The simulations were carried out at temperature 27 ºC. The power consumption of the proposed adders were minimized so that these adders can be used for low power applications.
Adder Architectures, CMOS, Low Power, Full Adder, Half Adder
