1Research Scholar, ECE Department, Saveetha School of Engineering, Saveetha University, Thandalam, Chennai
2Professor, ECE Department, Saveetha School of Engineering, Saveetha University, Thandalam, Chennai
Interconnect has happen to the dominating factor in the performance of determining circuit and dependability in the design of deep submicron designs. It is first discussed the patterns and challenges of interconnect design as the technology feature size quickly diminishes below 0.1 micron. At the point it is explained the regularly utilized interconnect models and an arrangement of interconnect design and optimization techniques for enhancing interconnect performance and reliability. At long last, the presentations are the comparisons of various optimization methods in terms of their efficiency and optimization results and demonstrate the impact of these enhancements. The output shows how the optimization carried over for DSM designs.
Interconnect, Delay, Submicron Optimization, Iterativesizing
