1Student, Saveetha School of Engineering, Saveetha university, Chennai
2Associate professor, Saveetha School of Engineering, Saveetha university, Chennai
The minimization of total power consumption using Efficient Charge Recovery Logic (ECRL) and Secured-Quasi Adiabatic Logic (SQAL) for low power adder architectures are proposed in this paper. They are implemented in CMOS 90nm Generic Process Design Kit (GPDK) technology library. The main objective of the propose technique is minimize the total Power consumption of a full adder using ECRL and SQAL based adder architectures are compared in this paper. These adders were simulated using Cadence Virtuoso Analog Design Environment (ADE) Electronic Design Automation Tool (EDA). The simulations were carried out at temperature 27 ºC. The power consumption of the proposed adders was minimized so that these adders can be used for low power applications.
Adder Architectures, Low Power, Ripple Carry Adder, Incremental Adder, Triangular Adder and CMOS
