1Student, Department of Electronics and Communication Engineering, Saveetha School of Engineering, Saveetha University, Chennai, India
2Professor, Department of Electronics and Communication Engineering, Saveetha School of Engineering, Saveetha University, Chennai, India
Online published on 16 January, 2018.
The timer for an ATM machine can be designed through a program, but that design does not facilitate parallel operations since programs execute sequentially and hence the timer has to be implemented in the chip level. The addition of a timer to the ATM processor can also meet the need but still there is no way to help the ATM machine to timeout when there is a software failure or no timeout signal to indicate its stuck state. So this can be sorted out using a Watchdog timer. Thus the objective is to design, implement and simulate a Watchdog timer for an ATM machine which acts as system supervisor. This implementation ensures that the ATM machine is in a safe state and restoring normal operation. The ATM machine makes use of this watchdog timer in situations where the system is hung and also when the user does not give any input. The system is being designed using HDL as it allows the behavior of the required system to be described (modeled) and verified (simulated) before the design is being translated into real hardware form.
ATM, FPGA, RTL, HDL and Integrated IC
