Design of low power johnson counter using lector technique using 50nm technology

Power dissipation is an important consideration in the design of CMOS VLSI circuits. In the case of battery-powered application, high power consumption leads to reduction in the battery life and affects reliability, packaging and cooling costs,. With technology processes advancing towards deep submicron and nano regimes, the scaling down of the threshold voltage levels in turn causes an exponential increase in sub threshold leakage currents leading to increase in leakage power. With the advance of each generation of the fabrication process a five-fold increase in leakage power dissipation is present. Leakage currents flow when the circuit is idle and so power is wasted. Efficient leakage power reduction techniques have become critical for the deep submicron and nanometre circuits. In this paper, a 4-bit Johnson counter is designed using LECTOR technique and is analyzed with different types of sleep techniques. We have used digital schematic editor (DSCH) for designing; simulation and layout generation is done using Micro wind Layout Editor.