Parallel hardware architecture for implementation of high speed MAC

Multiply and accumulation (MAC) is basic function in most of the signal processing applications like video, image processing, pattern recognition. Multipliers corresponding to the MAC unit are designed using combinational logic circuits. Modern computers consist of dedicated MAC unit and multiplication is usually performed using serial hardware which is referred as a unit cell. This MAC unit cell as supported in many architectures fail to meet the real time response for high rate data applications. The rationale of this paper is to propose parallel architecture for multiply and accumulate operation with high throughput rate. The proposed architecture performs the multiplication of operands involved in the MAC unit parallely and accumulates the result. The architecture also enables reusing of hardware for higher order taps based on the reusability factor. The functional units of the proposed architecture are developed at module level using RTL and behavior is simulated in Xilinx ISE 14.1 and synthesized on Virtex 7 family of FPGA. The obtained throughput for 128 taps is 16 MACs per cycle with reusability equal to 1 at clock frequency of 8.33 MHz for precision fixed to 8 bits.