Reduced tree Structure Based Multiplier Design

Expansion of standard mobile and wireless network communication applications have significant demands on signal processing. Traditional signal processing approaches are filtering, convolution, correlation, and transformation of signals. Among these methods, filters are widely used in wireless mobile and network applications to filter the services of incoming/outgoing users. The primary function of a filter is to selectively allow the desired signals to pass through and suppress undesired signals based on frequencies. In this work, the design of MAC unit by using the modified compound Wallace tree multiplier is presented. This new adder design is performed efficiently regarding the VLSI design environment compare than the traditional multiplier unit. Verilog HDL language is used to implement the proposed design.