Design of Pipelined Radix-2, 4 and 8 Based Multipath Delay Commutator (MDC) FFt

FFT processor of pipelined FFT consists of a sub-class of architectures that are determinedly efficient in hardware. The pipeline FFT is a special class of FFT algorithms which can calculate the FFT in a serial manner; it attains real-time behavior with non-stop processing when the data is continually fed through the processor. This algorithm needs less computation due to its recursive operator named butterfly. In this paper, the pipelined structure of Radix-2, 4 and 8 based Multipath Delay Commutator (MDC) FFT has been proposed for enhancing the throughput and speed. The pipelined architecture of multi path delay commutator (MDC) FFT is utilized for different length of OFDM system by putting the data stream of N_s at the input.