Design of Mixed Radix-2, 3& 4 based SDF-MDC FFT for OFDM Application

Pipelined architectures of Fast Fourier Transform (FFT), which are well-organized for long instances and it is significant for modern digital communication and radar systems. This paper present a design of Mixed Radix Fast Fourier Transform (FFT) processor for high speed DSP application like OFDM based communication systems such as digital audio and video broadcasting (DAB & DVB). The efficient design of mixed radix-2, 3 and 4 based Single path Delay Feedback (SDF)-Multipath Delay Commutator (MDC) FFT using MCSLA has been proposed for reducing the area and power consumption in this paper. An FFT using this algorithm is computed in an ordinary complex plane and the number of additions can be significantly reduced and the number of multiplication is also reduced. Modified carry select adder has been designed to reduce the hardware utilization. Finally, the MCSLA has been incorporated into mixed radix-2, 3 and 4 SDF-MDC FFT for improving the performance of architecture. The proposed architecture will be absolutely useful in OFDM based digital communication to perform the function of frequency transformation techniques. These architectures are designed by using ModelSim 6.3C tool and the synthesis results are evaluated by using Xilinx ISE 10.1 design tool.