Implementation of Pipelined Out Of Order Queue Processor Architecture

In conventional processors, programs are executing in order and if there any dependency happen between the instructions, the execution needs to wait till the dependencies is over. It will reduce the performance and restricts the expression of parallelism in the program. In general, the instruction that can be executed simultaneously will perform separately.

Queue computing model provides excellent support for the existing processor designs. The instructions in the queue computing model, is not having any register expression part and hence there is no dependency as in above case. In addition to that, the elimination of register expression part makes the instruction length shorter and the programming can be done very easily. Most of the current processors are using complex hardware structure for register renaming and it can completely avoided in queue computing model

The efficiency of the processor can easily be improved by using pipelining. Queue processor will support all the facilities that are provided by the modern processor architectures. This paper describes the implementation of queue processor architecture along with pipelining and out of order execution and compares their performances.