Hardware implementation of block-cipher scalable encryption algorithm

Secured communication of sensitive data has always been of prime importance in electronic devices. Information security, data integrity, confidentiality, authenticity and non-repudiation are the most important aspects of communication between electronic devices. The world today is moving towards embedded systems, increasing the need for information security with minimal resources. Scalable Encryption Algorithm (SEA) is one of the frontrunner to capture its share in embedded market. Scalable Encryption Algorithm is a parametric block cipher encryption technique used in resource constrained applications like sensor nodes and RFIDs as the main requirements of such applications are small code and memory size. In this paper, previous work on the Block-Cipher Scalable Encryption Algorithm and the advantages of SEA are compared to other light weight encryption algorithms are explained. The Scalable Encryption Algorithm design is tweaked to make use of 3-bit and 4-bit substitution tables and an eleven round, half-duplex, two substitution box SEA is implemented on Virtex-5 FPGA and verified using Xilinx Chip Scope Pro. The design is also implemented using embedded c programming language and tested on a microcontroller test board to check for its working in the real world.