Design and development of minimum-leakage standard cell library using MTCMOS technique for full custom power aware designs

The main objective of this work is to design a Low Power Standard Cell Library that contains a collection of components standardized at the logic or functional level. The technology is adopted for a channel length of 90nm and the supply voltage of 1V, for efficiency. The library is successfully designed with standard cells consisting of all logic gates with low leakage power incorporating the MTCMOS technique using the Cadence Tools, satisfying the design rules. The power dissipation is calculated for different cells of the library designed for minimum area, high speed and minimum leakage with different loads. The cells are designed to handle different loads by varying the size of the sleep transistor. After post layout simulation it is observed that there is a reduction in power dissipation up to 50% using the MTCMOS technique.