Implementation of High Performance Addressable Memory for Future Search Engines Using 45nm CMOS Technology

Power has become one of the most important paradigms of design convergence for multi gigahertz communication systems such as optical data links, wireless products, microprocessor & ASIC/SOC designs. Large capacity content addressable memory (CAM) is a key element in wide variety of applications, e.g. pattern matching and recognition in particular. Memory processing has been considered as the pace-setter for scaling a technology. A number of performance parameters including capacity (that relate to area utilization), cost, speed, active power consumption, standby power, robustness such as reliability and temperature related issues characterize memories. Memories such as Static RAM and conventional CAM have some problems related to above performance parameters. As if we compare these parameters of SRAM and CAM cells with Memristor based CAM (MCAM) cell, MCAM cell shows better performance parameters than other. The main problem of SRAM cell and CAM cell is that they cannot store the data when the power supply is turned OFF. But a cell with the use of memristor i.e. MCAM cell overcome this problem as it stores the data in the memory device as it is, even if the power supply is turned OFF.

This paper provides a new approach towards the design and modeling of memristor based CAM (MCAM) using a combination of MOS devices to form a core of a memory or logic cell that forms the building block of the CAM architecture. The non volatile characteristics and the nanoscaled geometry together with compatibility of the memristor with CMOS processing technology increases the packing density, provides for the new approaches towards power management through disabling CAM blocks without loss of stored data, reduces power dissipation, and has scope for speed improvement as the technology matures.