Design of 1, 024 × 16 cm⁸ SRAM Using Self-time and Other Power Reduction Techniques

SRAM design is very crucial as it takes a large fraction of total power and die area in high-performance processors. The performance of embedded memory and its peripheral circuits can adversely affect the speed and power of the overall system. This paper explores the design of SRAM focusing on optimising delay, reducing power and layout area. The key to low power operation of the design is self-timed architecture, multi stage decoding and full custom approach. A 1, 024 × 16 SRAM is designed using Predictive Technology Model BSIM 4 Bulk at 180 nm technology with 1 V power supply (V_DD). The aspect ratio that is W/L of the transistors used in an SRAM cell is taken in the range 0.6 < W/L < 1.8. Complete read/write, self-time and other simulations were carried to substantiate the techniques implemented in this paper.