Noise Tolerance Enhancement with Leakage Current Reduction in Dynamic Logic Circiuts

To improve noise tolerance of the dynamic logic circuits with leakage current reduction, a new noise tolerant technique is proposed here. Average noise threshold energy (ANTE) metric is used to compare the noise tolerance ability of the existing techniques with the proposed technique. A two input AND gate is designed and simulated using 0.18 micron technology and at a clock frequency of 100MHz. Simulation results indicate that the proposed technique provides an improvement of 77.72% in ANTE with a reduction of leakage current by 73.9% over the conventional domino technique.