Design of Low Voltage and Low Power D-Flip Flop

This paper presents a novel D flipflop for low The main difference between latches and flipflops is that for voltage operation with improved speed using SPICE latches, their outputs are constantly affected by their inputs as simulation, it takes advantage of a dynamic threshold voltage long as the enable signal is asserted. using DTMOS for ultralow voltage operation and a negative differential resistance storage using Bistable Gated Bipolar Device (BGB). DTMOS provides low power consumption and BGB provides high speed because of less capacitance. So we have taken advantages of both the DTMOS and BGB device to make the DFlip Flop for low power operation with high speed and low leakage current. Leakage is further reduced by addition of two sleep transistors.