International Journal of Scientific Engineering and Technology
  • Year: 2012
  • Volume: 1
  • Issue: 5

Employing Functional Analysis to Study Fault Models in VHDL

  • Author:
  • N Venkatesh Kumar1, Mujeeb Ulla Jeelani2, V Amritha Mulay3, Anoop S Shandilya4
  • Total Page Count: 2
  • Page Number: 207 to 208

1Asst. Professor, SET, JAIN University, Bangalore, Freelance Consultant and Trainer

2Software Engineer, 7Star Technologies, Bangalore

3Software Engineer, Allied Tools and Electronics, Bangalore

4Student, Signal Processing and VLSI, M. Tech, SET, Jain University, Bangalore

Online published on 4 November, 2017.

Abstract

In this paper, VHDL & functional analysis is used to model and to study the effect of faults on gate level circuits respectively. The model is developed via abstraction of industry standard single stuck line (SSL) faults into the behavioral domain and the effects of these faults on gate level circuits are discussed.

Keywords

Fault Models, Behavioral Modeling, VHDL, Functional Analysis, RTL Synthesis, Stuck Faults