International Journal of Scientific Engineering and Technology
  • Year: 2013
  • Volume: 2
  • Issue: 5

Analyzing Performance of VHDL-AMS for Switch Level Modeling and Simulation

  • Author:
  • A.B. Pooja, D.K. Nupur, S. S. Nisha, V. K. Prashant
  • Total Page Count: 5
  • Page Number: 438 to 442

Department of Electronics Engineering, Sardar Patel Institute of Technology, Mumbai, Maharashtra, India

*Email: bhavsarpooja@rediffmail.com

Online published on 4 November, 2017.

Abstract

VHDL-AMS (IEEE 1076.1–1999), an extension to the VHDL, is considered to be a unified language for digital analog, mixed-signal modeling [1], [2]. Although traditionally AMS language is commonly used for behavioral modeling, in this paper special emphasis is given to modeling of mosfet based devices at switch level. We have analyzed VHDL-AMS for switch level modeling on basis of accuracy and response time. It is demonstrated by comparing parameters of CMOS inverter, universal gates and full adder. For all circuits implemented at switch level mosfet used is level-3 MOS Empirical model validated in System Vision 5.9 from Mentor Graphics

Keywords

VHDL-AMS, modeling, MOSFET, simulation