This paper presents the design and implementation method of a Universal Asynchronous Receiver Transmitter (UART) as a widely used serial communication protocol using Verilog Hardware Descriptional Language (HDL). In order to achieve the needs of latest complex communication system demands, a UART controller has been designed using FIFO (First In First Out) buffer technique for asynchronous serial data transmission between systems. Also, this reduces the delay, synchronisation error between sub-systems and provides a reliable, high performance logic solution for complex systems. The simulation and synthesis has been carried out using Modelsim DE 6.5 (inc. Mentor Graphics).
UART, Verilog HDL, FIFO, synchronisation error, baud rate
