BIST Architecture and Implementation of 64-Bit Double Precision Floating Point Multiplier Using VHDL

In this paper a 64-bit double precision floating point multiplier is implemented. A BIST test pattern generator for double precision multiplier is proposed. Linear feedback shift registers are used to generate the test pattern. A comparator is used to compare the output response and the expected response. For the circuit to work correctly the output response must be the same as the expected response. Xilinx ISE is used to synthesize the circuit and ModelSim is used for simulation purpose.