This paper deals with low power ALU design and its implementation on 90nm Spartan 3 FPGA. Most of power is consumed in ALU in any processor and hence reduction in ALU power is needed. In this work, we have designed a low power ALU. To reduce dynamic power consumption we disabled the blocks which are not needed in currently selected operation. Also hardware is reused; this will cut down the FPGA resource usage and also reduce the power consumption. By using these methods dynamic power consumption is reduced and less FPGA resources were consumed.
FPGA, ALU, low power, Hardware reuse, tri-state logic, dynamic power consumption
