New Approach to Reduce Energy Consumption in Six Transistors SRAM

This paper presents the technique used to reduce significant energy savings (e.g. 59% to 76%) for the different the power dissipation in 6T SRAM. Normally there is a power 0.5μm SRAM parts at 200 MHz. loss in charging and discharging the bit line during reading In [VII] J. Kim et.al uses a dummy bit line capacitance and writing. This power loss is drastically reduced with the use with a constant load for each pair of bit lines in order to provide of additional adiabatic circuit. Simulation of the circuit is done a constant load to the charging source during all the operation using HSPICE in 65nm technology. This circuit also preserve cycles including hold cycles. They found that 53% of power is power during writing phase also. saved as compared to conventional SRAM at 400MHz and 2.5V during write cycle.