Toobtain the low power, delay reduction and high performance. In this paper, an analysis on the delay of both conventional dynamic comparator and conventional double tail dynamic comparator which are called clocked regenerative comparator will be presented. Designers can obtain an intuition about the main contributors to the comparator delay and fully explore the trade off in dynamic comparator design. Based on, a new dynamic comparator is proposed, where the circuit of a conventional double tail comparator is modified for low power and fast operation even in small supply voltages. Pre-layout simulation results in a 0.18-μm CMOS technology confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. Both delay and power consumption can be reduced by adding few transistors to the proposed comparator. The supply voltage of 0.8 V, while consuming 9μW in modified comparator and 12μW in proposed comparator respectively. Hardware was implemented in FPGA Kit using VHDL coding.
Double tail comparator, low power, fast operation, Pre-layout simulation, and FPGA
