1Guru Tegh Bahadur Institute of Technology, affiliated to Guru Gobind Singh Indraprastha University, New Delhi, India
Indira Gandhi Delhi Technical University for Women Kashmere Gate, New Delhi, India
In this paper, a technique integrating Oscillation and IDDQ based test methodology for two stage CMOS operational transconductance amplifier is presented. The approach is attractive for its simplicity, robustness of oscillation based test technique that needs no test signal generation and combines it with quiescent supply current testing which utilized the built in current sensor to monitor quiescent current changes without performance degradation of the circuit under test. Both short and open faults are detected by this test methodology. Simulation results for two stage operational transconductance amplifier using a 0.18μm n-well CMOS technology show that the proposed combined test strategy has 100% fault coverage and capability of built-in-self test implementation. It can also be used as generalized test structure for other CMOS analog and mixed-signal integrated circuits.
Operational transconductance amplifier (OTA), Circuit under test (CUT), Monte-Carlo simulation, faults, OTM, BICS