Invertis Journal of Science & Technology
  • Year: 2013
  • Volume: 6
  • Issue: 4

Role of High-k Materials in Nanoscale TM-DG MOSFET: A Simulation Study

  • Author:
  • K.P. Pradhan, P.K. Agarwal, P.K. Sahu, S.K. Mohapatra
  • Total Page Count: 5
  • Page Number: 195 to 199

National Institute of Technology, Rourkela (Odisha)

*E-mail: kp2.etc@gmail.com

Online published on 5 August, 2015.

Abstract

Triple Material (TM) Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with high-k dielectric material as Gate Stack (GS) is presented in this paper. The high-k dielectric materials as Si3N4 (ε=7.5), HfO2 (ε=20) and TiO2 (ε=40) is sandwiched over a low-k SiO2 (ε=3.9) layer. We investigated the parametrs like Surface Potential, Electric field in the channel, Sub threshold Swing (SS), Drain Induced Barrier Lowering (DIBL), Transconductance (gm), on current (Ion), leakage current off current (Ioff) for TM-DG and TM-GS-DG and a close comparison is made between them. The ability of suppressing the short channel effects (SCEs) in case of TM-GS-DG over TM-DG MOSFET is also discussed in this paper. The simulation and parameter extraction have been done by using the commercially available device simulation software ATLASTM.

Keywords

DG-MOSFET, SCEs, gate stack (GS) engineering, work function engineering, ATLASTM device simulator