Impact of Insulating Layers on Single and Double Gate MOSFET for Improved Short Channel Effect and Hot Carrier Reliability

In the present work, Gate edge charges related issues of various un-conventional device architecture has been analyzed for low voltage analog applications using 3D numerical simulation. The accuracy of the simulated results is verified by an excellent match between simulated and experiment results of DG MOSFET. The impact of gate edge charges on short channel effects i.e. (i) threshold voltage, (ii) sub-threshold slope, (iii) on-current I_on, (iv) I_on/I_off ratio and analog performance metric i.e. (v) Early voltage (V_ea), (vi) Output Resistance (R_out), (vii) Trans-conductance (g_m), (viii) Trans-conductance generation efficiency (g_m/I_ds) and (ix) On-state Resistance (R_on) is analyzed by exhaustive device simulation. Results show that Dielectric Pocket Double Gate (DP-DG) MOSFET and Empty Space in Double Gate (ESDG) MOSFET can not only effectively control the short channel effects and provide excellent analog and digital performance but can also be optimized to achieve better hot carrier immunity because of the existed gate edge charges as compared to conventional Double Gate (DG) MOSFET and their corresponding single gate architectures i.e. Dielectric Pocket (DP) and Empty Space in Silicon (ESS) MOSFET.