1Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi, South Campus, New Delhi-110 021
2Department of Electronics, Deen Dayal Upadhyaya College University of Delhi, New Delhi-110 015
3Department of Electronics and Communication Engineering, Maharaja Agrasen Institute of Technology, Sector-22, Rohini-110 086, Delhi
*E-mail: rakhinarang@gmail.com
Online published on 5 August, 2015.
In the present work, a detailed study of Silicon based Nanowire (NW) tunnel FET (conventional p-i-n and pocket doped p-n-p-n) has been carried out and the various analog and digital parameters have been investigated and compared with that of MOSFET. The digital performance has been assessed on the basis of, threshold voltage, Ion/Ioff and ambipolar characteristics and analog performance in terms of device efficiency gm/Ids and cut-off frequency (fT). Further, the lengths of high-k and low-k gate dielectric in a hetero-gate (HG) dielectric TFET architecture have been optimized in order to obtain high ON current, low off current, suppressed ambipolar behavior and low parasitic capacitances and thus an optimum device performance.
Nanowire, p-i-n, p-n-p-n, tunnel field-effect transistor
