Design of 4–2 and 5–2 Compressor with 14T Full Adder

In this paper new designs of low power 4–2 and 5–2 compressors circuits have been reported using 14 transistors (14T) full adder circuit. Compressors are critical component of the multiplier circuit and significantly influence the overall multiplier speed. A 4–2 compressor circuit designed with 14T adder shows power consumption of 578.87 pW with maximum delay of 611.27 ps. Further 5–2 compressor circuit shows power consumption of 595.92 pW with maximum output delay of 885.74 ps. Simulation has been carried out using SPICE based on TSMC 0.18μm CMOS technology. The proposed compressor circuits have been compared with earlier reported circuits in terms of power consumption, delay and power delay product (PDP). Present circuits have improved performance as compared to previous circuits.