Effects of Barrier Layer of Nanoscale InGaAs-Channel MOSFETs on Analog Circuit Performance

In recent years MOSFETs using an InGaAs channel have attracted much attention for high performance logic applications due to enhanced electron mobility, which is known to further improve with the incorporation of a barrier layer on top of the channel. In this paper, using extensive device simulation we present a comprehensive report concerning the impact of a barrier layer on the analog performance of In_0.7Ga_0.3As nMOSFETs in the terms of transconductance, transconductance efficiency, output conductance and intrinsic gain for channel length down to 20 nm. It is found that different device parameters associated with analog applications such as ON-current, transconductance and gain exhibit considerable improvement for InP barrier thickness of 0.7 nm at channel length of 40 nm. Studies are extended to InGaAs devices without a barrier and also to Si devices for different channel lengths such as 40 nm, 30 nm and 20 nm. In all the cases InGaAs devices exhibit enhanced performance as compared with their Si counterparts. Furthermore, InGaAs devices with a thinner barrier ∼0.7 nm show better performance for analog circuit applications at the more advanced nodes.