1Department of Radio Physics and Electronics, University of Calcutta, 92 Acharya Prafulla Chandra Road, Kolkata-700009, India
2Department of Electronic Science, University of Calcutta, 92 Acharya Prafulla Chandra Road, Kolkata-700009, India
Recently hybrid Complementary Metal Oxide Semiconductor (CMOS) devices built using Ge-channel p-MOSFETs and InGaAs-channel n-MOSFETs have shown promise for high performance logic applications. In this paper, we have studied the performance of seven important logic gates such as AND, OR, NOT, NAND, NOR, XOR, XNOR, designed using both hybrid CMOS inverters and Si-based CMOS inverters having channel length of 45 nm. Different performance parameters of various logic gates such as rise time, fall time and gate delay are evaluated using extensive device simulations. The gate delay for the NOT gate built using hybrid CMOS exhibits an improvement of 78% as compared with that designed with Si CMOS. For the universal gates like NAND and NOR built with hybrid CMOS, the percentage improvements in the gate delay are found to be 74% and 72% respectively, relative to their Si counterparts. Additionally, the rise time and fall time of such gates with hybrid CMOS show the reduction of 96% and 75%, respectively over the corresponding equivalent Si logic gates. Our investigations reveal that all the performance parameters of logic gates built using hybrid CMOS show significant improvement as compared with those of Si based gates.
CMOS inverter, Ge p-MOSFET, InGaAs n-MOSFET, Rise time, Fall time, Propagation delay
