INROADS- An International Journal of Jaipur National University
  • Year: 2016
  • Volume: 5
  • Issue: 1s

Performance Analysis of NOC and Bus-Based Architecture

1Reasearch Scholar, Department of ECE, JNU, Jaipur, Rajasthan, India, Email id: shrivastavaanurag@rediffmail.com

2Professor, Department of ECE, JNU, Jaipur, Rajasthan, India, sudhir.732000@gmail.com

Online published on 2 August, 2016.

Abstract

A number of research studies have demonstrated the feasibility and advantages of Network-on-Chip (NOC) over traditional bus-based architectures. This paper tells the limitations of traditional bus-based approaches, introduces the advantages of the generic concept of NOC, and provides specific data about Arteris’ NOC, the first commercial implementation of such architectures, using a generic design. For example, we provide detailed comparisons of scalability, performance and area of traditional busses or crossbars vs. Arteris’ NOC.

Keywords

Bus-enhanced Network-on-chips, Buses, NOC Architectural