Modeling A FM Receiver With Digital Demodulator

In this paper we model and co-simulate a FM receiver with a Digital Demodulator with help of Matlab Simulink and Xilinx System Generator. As the RF signal received from antenna is analog, we model a superheterodyne front end which is then followed by a analog to digital converter, both are modeled in Matlab Simulink and SimRF, the Digital Demodulator is implemented using VHDL and integrated with the ADC module using Xilinx System Generator. The two designs are then co-simulated and the demodulated output is plotted in Matlab Simulink. The Digital Demodulator Model is implemented on FPGA Board. The modeling is useful while designing Software Defined Radios and compare various Digital Demodulator designs following the modeled rf front end and ADC.