1Research Scholar, School of Electronics, KIIT University>, Bhubaneswar, Odisha, India
2Associate Professor, School of Electronics, KIIT University, Bhubaneswar, Odisha, India
3Associate Professor, Electronics and communication Department, Anurag Group of Institutions, Hyderabad, Telangana
*Corresponding author email id: neeruniraj@gmail.com
Online published on 31 May, 2019.
The continuous scaling of CMOS (Complementary Metal-Oxide-semiconductor) technology exponentially increases the power density per unit area (means temperature) and other effects such as lifetime reliability. Bias temperature instability (BTI) is the serious effect which originates due to scaling of MOS, the effect of BTI on the design of SRAM (Static Random-Access Memory); it decreases the static noise margin (SNM) of the SRAM. In this paper, a prototype BTI sensor is proposed, which is used for correction of SNM of SRAM. It is designed on 15 nm technology and simulated in Hspice in Cadence 6.15; the precision found after simulation is under 1.15 mV (±3% approx) for 1-V supply.
Bias temperature instability (BTI), Reliability, SRAM, Static noise margin (SNM) degradation, Cadence, H-spice