FPGA Implementation of RSA Encryption and CRT based Decryption using Parallel Architecture

This paper aims at implementing Rivest Shamir Adleman (RSA) Encryption and Decryption Engine using Fast Modular Exponentiation (FME) Algorithm on FPGA. It supports multiple key sizes of 256 bits, 512 bits and 1024 bits. Choosing a large value of decryption key will reduce the threat of any forms of cryptanalysis. The proposed Encryption Engine is implemented using FME Algorithm and the decryption Engine is implemented in a parallel architecture using Chinese Remainder Theorem (CRT) which decreases its processing time on the FPGA. VHDL code is synthesized and simulated using Xilinx-ISE

13.4. Hardware implementation is performed on Xilinx Virtex-6 FPGA XC6VLX240T-3ff1156 and the verification of the results is performed by using Chip Scope Pro Tool. Implementation results show that for a 16-bit RSA, decryption speed has improved significantly compared to my previous model. Hence, computation time has been improved quite noticeably by introducing a parallelism into architecture.