Development of a reconfigurable ip standardizing environment for axi decoder

AMBA [Advanced Microprocessor Bus Architecture] bus model is one of the prominent bus architectures used in System-on-Chip designs. The bus protocols support a chunk of address region, which expects the blocks that support the protocol should possess the address space/region within the boundary supported by the protocol. To know the exact region of the address space which the master needs to communicate with a module, is used in between the bus interface and the slave interface. The module is called as ADDRESS DECODER. These address decoders are unique to the bus protocol.

In the current paper, the design algorithms followed to support the AXI protocol have been examined. The address decoding technique that decodes the valid and exact address of a slave is designed. The master communicates to slave by generating the valid strobes only if the slave error or the decode error doesn't exist. The decoded address represents the registers for valid strobes present in the CSR/Memory Map. Based on the strobes generated the data transactions occur. The tools used are Cadence NC-Sim for simulation and RTL Encounter for synthesis.

The AXI address decoder has been designed using two parallel FSMs and the simulations are observed in Cadence NC-Sim. The design supports an interleaving depth of 1. The design supports burst length of 16 and a maximum data width of 1024 bits. The maximum address space by the address decoder is 4KB as supported by protocol. The address types that are supported by the design are FIXED, INCREMENT and WRAP. The maximum operating frequency of the top-level AXI Address Decoder works at 156.674MHz meeting the design specification of the protocol. From the simulation we conclude that the address decoding technique can successfully identify the slave address in the AXI protocol under the design specifications.