SASTech - Technical Journal of RUAS
  • Year: 2011
  • Volume: 10
  • Issue: 2

High speed memory efficient 3d discrete wavelet transform for surveillance system

  • Author:
  • P. Sreenath, P. Cyril Prasana Raj
  • Total Page Count: 5
  • Page Number: 1 to 5

VLSI System Design, M. S. Ramaiah School of Advanced Studies, Bangalore, 560 054, India Email: cyril@msrsas.org

Online published on 18 February, 2020.

Abstract

The DWT based image compression technique leads into a new era of video and image processing with its better peak signal to noise ratio and high scalability in compression. The 3D DWT on video brings up the new possibilities in advanced fields like medical imaging, hyper spectral imaging, satellite based 3D surveillance system and video on network. The 3D DWT is still far from the real time applications because of its huge requirement of memory and computational complexity. The realization of 3D DWT in hardware is the best option to overcome the hurdles of computational speed. The requirement and management of large amount of temporary memory is the toughest problem which keeps the 3D DWT far away from the best choice as an image or video compression technique.

In the current paper work, a novel high speed 3D DWT architecture has been presented with efficient memory management and parallel processing techniques. The proposed architecture computes one level spatial transform on nine image frames concurrently and temporal transform following, this is realized with nine 2D DWT and four 1D DWT processors associated in parallel. The simultaneous transform on nine frames and a novel “window scan and slice” scheme and “hold and push” memory management techniques reduces the memory requirement drastically. A memory efficient DA based 9/7 Daubechies filter bank has been developed for the suitable implementation of 3D DWT on FPGA and it improves the speed of the 3D DWT.

From the study we find that the proposed 3D DWT architecture can deliver samples at about a 16% higher clock rate, with just over half the resource utilization. We thus conclude that the proposed architecture is significantly superior to existing 3D DWT architectures.

Keywords

3D DWT, Concurrent Processing, Memory Management, DA, 9/7 Daubechies and FPGA